Saddle type mos device

ABSTRACT

The present invention relates to a nano-scale MOS device having a saddle structure. Particularly, the invention relates to a high-density, high-performance MOS device having a novel structure capable of improving the scaling-down characteristic and performance of the MOS device, in which a channel and gate structure is formed in the shape of a saddle. The inventive MOS device is mainly characterized in that a channel region is recessed, a gate insulating film and a gate electrode are formed on the surface and sides of the recessed channel, and the gate electrode is self-aligned with the recessed channel. Namely, in the disclosed MOS device, a portion of the insulating film around the recessed channel is selectively removed to expose the surface and sides of the recessed channel. According to the present invention, the scaling-down characteristic of the device is excellent and current drive capability is greatly increased since a channel through which an electric current can flow is formed on the surface and sides of the recessed channel. Also, the ability of the gate electrode to control the channel is enhanced. Accordingly, the invention can improve device characteristics.

TECHNICAL FIELD

The present invention relates to a nano-scale MOS device having a saddlestructure. More particularly, it relates to a highly integrated,high-performance MOS device having a novel structure capable ofimproving the scaling-down characteristic and performance of the MOSdevice, in which a channel and gate structure is formed in the shape ofa saddle.

BACKGROUND ART

Recently, the gate size of devices in CMOS technology has been reducedto less than 100 nm, and devices for high-speed logic and memoryapplications have been actively developed. In MOS devices for logicapplications, the thickness of a gate insulating film can be reduced to2 nm or less, and thus so-called short-channel effect can be suppressed.The MOS devices can be applied in various fields such as CPU and logic,although they have some short-channel effects.

However, in DRAM applications, the thickness of the gate insulating filmmust be at least 5 nm. Although this thickness can decrease according tothe development of technology in future, it will be difficult todecrease greatly. Thus, since the gate insulating film in MOS devicesfor DRAM application can be reduced only to a limited extent as comparedto that in devices for logic applications, the existing MOS deviceshaving a planar channel have a severe short-channel effect.

One of methods capable of solving this problem is to recess a channelregion. In the structure having the recessed channel region, theshort-channel effect can be improved as compared to the existing planarchannel MOS devices. Also, the sensitivity of threshold voltage to thedoping concentration or profile of corner regions formed at the bottomof the recessed channel are very high, even when the corner regions aremade round. Furthermore, in these recessed devices, a change inthreshold voltage due to substrate bias is much greater than in theexisting planar channel structure, and the effective channel length isincreased due to the channel recess. Thus, the recessed structures havea shortcoming in that, if the channel width becomes narrower, thecurrent drivability will be greatly reduced. The general feature of therecessed channel devices is that the gate electrode is inferior in itsability to control the channel to that in the planar channel devices.This is associated with a large substrate bias effect.

The case where a gate electrode is excellent in its ability to control achannel is a double/triple-gate MOS structure, in which the gate wrapsthe channel region. The present inventors developed, for the first timein the world, a body-tied double/triple-gate MOS structure (KoreanPatent Application No. 2002-5325, Japanese Patent Application No.2003-298051, and US Patent Application No. 10/358981) and theapplication thereof to flash memories (Korean Patent Registration No.0420070 and U.S. patent application Ser. No. 10/751860, and named thisstructure “bulk FinFET”.

In this structure, the channel is not recessed, and is formed either onthe surface and both sides of the active body or on both sides of thebody, so that the structure is much superior in the ability of the gateto control the channel to the existing planar channel devices, and has avery small substrate bias effect. However, in order to suppress theshort-channel effect, the body width must be about ⅔ of physical gatelength. This means formation of a silicon body having a width narrowerthan the minimum gate length, causing a process problem.

Meanwhile, the existing planar channel MOS devices with a gate length ofless than 100 nm show various problems in scaling down. It is reportedthat the existing planar channel device can be currently scaled down toa gate length of less than 50 nm, and the scaling down of the existingplanar channel device structure encounters the problem of so-calledshort-channel effect. Generally, with the scaling-down of devices, thethickness of the gate insulating film can also be reduced, and thus theshort-channel effect can be suppressed partly. In MOS devices for logicapplications, the thickness of the gate oxide film can be reduced toless than 2 nm, so that the short-channel effect resulting from areduction in the gate length can be somewhat suppressed. MOS deviceshaving a little short-channel effect can be used for logic circuitapplications.

With the scaling down of MOS devices for logic applications, the channellength of devices for dynamic random access memory (DRAM) applicationsdecreases to less than 70 nm, while these devices encounter largerdifficulty in scaling down than those for logic applications. In MOSdevices for DRAM applications, since the thickness of the gateinsulating film is generally about 5 nm or thinner, the above-mentionedshort-channel effect is not effectively suppressed. If the operatingvoltage of DRAM and the thickness of the gate insulating film arereduced at a given gate length, the scaling-down at a gate length ofless than 70 nm seems likely to be possible. However, according togeneral scaling rule, the scaling down of DRAM devices with conventionalplanar channel structure seems to be difficult, and a change in devicestructure to solve this difficulty is required.

A case where a device, fabricated by simply etching a channel to make arecessed channel and forming a gate insulating film and then a gateelectrode is applied to DRAM, was proposed by Samsung Electronics Co. inthe year 2003 (J. Y. Kim et al., “The breakthrough in data retentiontime of DRAM using recess-channel-array transistor (RCAT) for 88 nmfeature size and beyond”, in Proc. Symp. on VLSI Tech., p. 11, 2003).

Disclosure of Invention Technical Problem

In the prior art as shown in FIG. 1, the recess depth of the recessedchannel can be made deep. This can increase the effective channellength, resulting in suppression of the short-channel effect. However,since the effective channel length is long, this device has ashortcoming in that, if the channel width of the device is decreased toincrease integration density, the current drive ability of the devicewill be significantly reduced. In addition, this device has shortcomingsin that two comers (or rounded bottom) clearly appear in the recessedchannel region in the channel length direction, and if the channeldoping concentration around these corners (or rounded bottom) is changedeven a little, threshold voltage will be greatly changed. In thisdevice, the doping concentration is increased generally near the bottomof the recessed channel region.

Since recess-channel devices generally have a concave channel structure,they have problems in that the back-bias effect seriously occurs and,for example, the threshold voltage of NMOS devices greatly increases fora negative (−) back bias.

Technical Solution

Accordingly, the present invention has been made to solve theabove-mentioned problems, and it is an object of the present inventionto provide a MOS device which overcomes problems with the existingrecess-channel devices, including a reduction in current drivecapability resulting from a reduction in the effective width of achannel, a large change in threshold voltage resulting from a change indoping concentration in the corner regions (or bottom) of the recessedchannel, a high back-bias effect and the like, while having high currentdrive capability and excellent subthreshold swing, even when theeffective width of the channel becomes smaller.

Another object of the present invention is to provide a MOS devicehaving side channels formed by a method in which a nitride film (or ainsulator with etch selectivity) around a recessed silicon body isselectively etched so as to be aligned in a recessed channel region,such that the sides of the recessed silicon channel are clearly exposed.

Advantageous Effects

As described above, the present invention can realize a MOS device inwhich a channel and gate structure is in the shape of a saddle.

Because the saddle-type MOS device structure according to the presentinvention has a recessed channel structure and a triple-gate structure,it has all the advantages of the existing double/triple-gate MOSFETs andthe advantages of the recessed channel MOSFETs. In addition to theseadvantages, the present invention provides the following additionaladvantages.

The existing bulk FinFET requires a fin body width corresponding to ⅔ ofthe gate length, whereas the inventive structure has no problem evenwhen making the body width equal to the gate length or thicker, and canprovide the advantages intended in the present invention.

Also, side channels can be formed by selectively etching a nitride film(or a insulator with etch selectivity) around a recessed channel regionto precisely expose the sides of the recessed channel region.

Moreover, although the channel is recessed, the gate electrode in theinventive structure is excellent in its ability to control the channelsince the gate is formed on the surface and the sides of the recessedregion. Also, the inventive structure can reduce a change in thresholdvoltage resulting from back bias, and reduce a change in thresholdvoltage resulting from a change in impurity concentration in the cornerregions (or bottom) of the recessed channel region. In addition, sincethe channel is formed on the surface and sides of the recessed channelregion, the inventive structure can have high current drive capability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the structure of a recess-channel MOS device according tothe prior art.

In FIG. 1, (a): a top view; (b): a three-dimensional perspective view;(c): an A-A cross-sectional view; and (d): a B-B cross-sectional view.

FIG. 2 shows the structure of a saddle-type MOS according to the presentinvention. In FIG. 2, (a): a top view; (b): a three-dimensionalperspective view; (c) an A-A cross-sectional view; and (d): a B-Bcross-sectional view.

FIG. 3 shows the structure of a MOS device according to a modifiedembodiment of the present invention. In FIG. 3, (a): a top view; (b): athree-dimensional perspective view; (c) an A-A cross-sectional view; and(d): a B-B cross-sectional view.

FIGS. 4 a and 4 b show the cross-sectional structure of the gateelectrode shown in FIG. 2.

FIG. 5 shows a cross-sectional structure view taken along the center ofthe nitride film shown in part (a) of FIG. 2. In FIG. 5, (a): a topview; (b) an A-A cross-sectional view; and (c): a C-C cross-sectionalview.

FIGS. 6 a to 6 c show that the corners between the surface sides of arecessed channel region in the structure shown in part (d) of FIG. 2 aremade round.

FIGS. 7 a to 7 f show a first embodiment of a process for making the MOSstructure of FIG. 2.

FIGS. 8 a and 8 b show a second embodiment of a process for making theMOS structure of FIG. 2.

FIGS. 9 a and 9 b show a third embodiment of a process for making theMOS structure of FIG. 2.

FIGS. 10 a to 10 c show an embodiment of a process for making regions 1,2 and 5 for making the inventive silicon body structure.

DESCRIPTION OF REFERENCE NUMERALS USED IN THE DRAWINGS

1: silicon substrate; 2: wall-type silicon body;

3: first insulating film; 4: first nitride film;

5: second insulating film (field insulating film or isolating insulatingfilm);

6: amorphous silicon (or polysilicon); 7: gate insulating film;

8: gate electrode (or self-aligned gate electrode);

9: source/drain regions; 10: spacer;

11: third insulating film; and 12: fourth insulating film.

BEST MODE FOR CARRYING OUT THE INVENTION

In a technical concept to achieve the above objects, the presentinvention provides a MOS device comprising: a silicon substrate I havingformed thereon a wall-type silicon body 2 connected with the substrate;a first insulating film 3 formed on the surface of the silicon substrate1 and the surface of the silicon body 2; a nitride film 4 formed on thefirst insulating film 3; a second insulating film 5 for elementisolation formed on the nitride film 4; a region to be used as achannel, which is recessed from the surface of the silicon body 2 to agiven depth; the nitride film 4 and the first insulating film 3 beingaligned to the recessed silicon body and etched more than the recesswidth or depth of the silicon body 2; a gate insulating film 7 formed onthe surface and sides of the recessed silicon body 2; a gate electrode 8and a spacer 10 sequentially formed on the resulting structure; andsource/drain regions 11 formed to a depth in the silicon body 2 on bothsides of the gate electrode 8.

In another embodiment, the present invention provides a MOS devicecomprising: a silicon substrate 1 having formed thereon a wall-typesilicon body 2 connected with the substrate; a first insulating film 3formed on the surface of the silicon substrate 1 and the surface of thesilicon body 2; a nitride film 4 formed on the first insulating film 3;a second insulating film 5 for element isolation formed on the nitridefilm 4; a region to be used as a channel, which is recessed from thesurface of the silicon body 2 to a predetermined depth; the secondinsulating film 5 being, if necessary, recessed from the surface thereofto a predetermined depth; the nitride film 4 and the first insulatingfilm 3 being aligned to the recessed silicon body 2 and etched more thanthe recess width or depth of the silicon body 2; a gate insulating film7 formed on the surface and sides of the recessed silicon body 2; a gateelectrode 8 and a spacer 10 sequentially formed on the resultingstructure; and source/drain regions 11 formed to a depth in the siliconbody 2 on both sides of the gate electrode 8.

Mode for the Invention

Hereinafter, the construction and operation of embodiments of thepresent invention will be described in detail with reference to theaccompanying drawings.

FIG. 2 shows a saddle-type MOS device according to the presentinvention. FIG. 2 c is an A-A cross-sectional view taken along theactive region in FIG. 2 a. FIG. 2 d is a B-B cross-sectional view takenalong the control electrode formed in the recessed channel region inFIG. 2 a. Also, the three-dimensional device structure shown in FIG. 2 bshows important parts except for metal interconnections or source/draincontact regions. FIG. 2 shows a structure obtained just after forming acontrol electrode and source/drain regions, and subsequent steps are thesame as CMOS processing technology. In FIG. 2 b, region 1 is a siliconsubstrate, and region 2 is a wall-type silicon body in which an activeregion is formed. The thickness of the wall-type silicon body 2 issuitably selected in a range of 3-100 nm. Region 3 is a first oxide film(or insulating film) having a thickness of 1-20 nm. Region 4 is anitride film, the thickness of which can be adjusted depending on agiven technology level and may vary in a range of 1-200 nm. The presenceof this nitride film is useful in clearly exposing the sides of therecessed silicon body in a subsequent process step. Namely, when thesilicon body 2 is recessed and then the nitride film of region 4 isselectively etched in a suitable process sequence, the sides of therecessed silicon body, covered with the thin insulating film 3, will beexposed and when the thin insulating film 3 is removed, the sides of therecessed silicon body can be clearly exposed. If the nitride film ofregion 4 is not present or used, the insulating film-around the recessedsilicon body 2 must be etched in order to expose the sides of therecessed silicon body 2. In this case, there is a problem in that thewidth of the side channels to be exposed cannot be precisely controlled,since the boundary between the exposed silicon and the remaininginsulating film may not be clear depending on the etching properties ofthe insulating film.

Region 5 corresponds to a field insulating film or isolating insulatingfilm for isolation between elements, and the thickness thereof isselected in a range of 50-1000 nm. Region 7 is a gate insulating filmwhich is formed on the surface and exposed sides of the recessed channelto a thickness ranging from 0.5 nm to 15 nm. Region 8 represents a gateelectrode, which has a thickness of 2-500 nm and may be made ofamorphous silicon or polysilicon, amorphous SiGe or poly-SiGe, metalshaving various work functions, silicide, or a combination thereof. Inthe structure shown in FIG. 2, the width of the gate electrode formed inthe recessed region may be the same or somewhat different from the widthof the gate electrode formed thereon (d7 in FIG. 2). Part (a) of FIG. 2shows the upper side (top view) of part (b), a three-dimensional view.In part (a) of FIG. 2, distance d1 is a distance obtained by etching thenitride film of region 4 with respect to the edge of the recessed activeregion so as to make the etched portion larger than the width of therecessed region of the active silicon body 2, thus resulting the gateelectrode to surround the sides of the channel. Distance d1 is in arange in 1-200 nm. In (c) of FIG. 2, d2 represents the height of thegate electrode protruded upward from the surface of the active siliconbody. The protruded height is in a range of 1-300 nm.

In part (c) of FIG. 2, d3 represents the depth recessed from the surfaceof the active region and is in a range of 10-300 nm. In part (d) of FIG.2, the corners of the recessed region can be made angular or round,according to application. In part (d) of FIG. 2, d4 is associated withthe thickness of the nitride film 4 and represents the width of the gateelectrode surrounding the sides of the channel. d4 is in a range of3-200 nm. In (d) of FIG. 2, d5 has essentially the same size as d1 shownin FIG. 2 a, and represents the distance by which the sides of therecessed channel are exposed. In some cases, the exposed distance of theside channel in the depth direction in the recessed channel region maybe made larger than the distance d1 on the surface.

After forming the structure as shown in part (b) of FIG. 2, a spacer 10may be formed around the gate electrode 8. The width of the spacer 10can be made larger than the sum of distance d1 shown in FIG. 2 a and thethickness of the gate insulating film 7. By doing so, in a subsequentprocess of filling a metal wiring material in a contact hole formedafter forming an insulating film, the metal wiring material can beprevented from forming short circuits with the gate electrodesurrounding the side channels. Thus, it can effectively increaseintegration density.

FIG. 3 shows a slight modification of the structure shown in FIG. 2. Thedifference from FIG. 2 is the cross-sectional shapes of regions 5 and 8shown in the right side of part (b) of FIG. 3. In FIG. 3, a gateelectrode in the field insulating film of region 5 is formed togetherwith the gate electrode around the recessed silicon body as self-alignedmanner. The self-aligned gate electrode is made by recessing thewall-type silicon body 2 to be formed with a channel, removing theinsulating film of region 3 and the nitride film of region 4 on bothsides of the recessed silicon body to expose side channels, andrecessing the field insulating film of region 5.

Part (a) of FIG. 4 illustrates that pluralities of wall-type bodies 2are formed in the structure of FIG. 2, and shows a cross-sectionalstructure between the wall-type silicon bodies 2 having a close intervaland the silicon bodies having a long interval, taken along the controlelectrode. As shown in the right side of part (b) of FIG. 4, in the casewhere the interval between the silicon bodies 2 is long, the thicknessof the initially formed isolating oxide film 5 is maintained almostintact. The minimum interval between the wall-type bodies 2 can be equalto the minimum body width (3 nm). The interval can be changed bytrimming a process for body formation or changing the distance inphysical layout. Referring to the left side of part (a) of FIG. 4, theinterval between the silicon bodies 2 can be seen to be close. In thiscase, since the total width (d8 in FIG. 4) of insulating films betweenthe silicon bodies is small, the isolating insulating film 5 is removedduring etching after recess so that the isolating insulating film 5 isformed lower than the surface of the recessed silicon body. A structureshown in part (b) of FIG. 4 corresponds to the structure of FIG. 3 hasthinner field insulating film of region 5 than that shown in part (a) ofFIG. 4 because region 5 is recessed to a suitable depth. In thisrespect, the isolating insulating film 5 between the silicon bodiesclose to each other is thinner in the horizontal direction than in thevertical direction, and is easily etched according to theabove-described principle so that the surface thereof is formed lowerthan the surface of the recessed silicon bodies.

Part (b) of FIG. 5 is a cross-sectional view taken along the center ofthe nitride film of region 4 formed on the side of the wall-type siliconbody 2 in part (a) of FIG. 2, and part (c) of FIG. 5 is across-sectional view taken across the gate electrode on the isolatinginsulating film. In part (b) of FIG. 5, since the recess width (d9 inFIG. 2) of the nitride film of region 4 is made larger than the recesswidth (d10 in FIG. 2) of the silicon body by selective etching, thewidth (d11 in FIG. 5) of the gate electrode in the recessed nitride filmregion is made larger than the protrusion width (d7 in FIG. 2). Ifprocess conditions are changed, the width of the gate electrode formedon the surface of the silicon body can be made larger.

In part (c) of FIG. 5, since the isolating insulating film of region 5is not intentionally etched in a recess form, the gate electrode 8 isformed only on the surface of region 5. In parts (b) and (c) of FIG. 5,a spacer of region 10 is shown in the form of a dashed-line, and isformed after forming the gate electrode. The suitable width of thespacer 10 is preferably larger than the sum of d1 shown in FIG. 5 a andthe thickness of the gate insulating film. In part (b) of FIG. 5, if thegate electrode 8 buried in the nitride film 4 causes stress with thenitride film 4, an insulating film can be formed between the nitridefilm 4 and the gate electrode 8.

FIG. 6 shows the cross-sectional structure of a wall-type silicon body2, taken along the gate electrode at a point where the gate electrode 8and the silicon body 2 in the structure of FIG. 2 meet each other. Thecorners formed along the surface of the recessed silicon body of region2 are made round so as to be able to prevent the concentration ofelectric field from the gate electrode, thus improving the reliabilityof the device. Also, parasitic channels being able to be formed alongthe corners can be removed to reduce leakage current.

In part (b) of FIG. 6, the corners of the recessed silicon channelregion are made round, and the body width becomes gradually largertoward the substrate of region 1 so as to be able to reduce theresistance of the body. In part (c) of FIG. 6, the corners of therecessed silicon body are made round, and the body of region 2 ismaintained almost vertical around channels, including side channels, andis gradually larger below thereof.

FIG. 7 shows one embodiment of a method for making the MOS devicestructure shown in FIG. 2. FIG. 7 shows key process steps to beprocessed after a body in which a channel is formed, and deviceisolation in the form of STI (Shallow Trench Isolation), are made, andthe surface is planarized. In this case, the method can be carried outin a state where some oxides have been formed on the surface of thesilicon body.

Part (a) of FIG. 7 shows a planarized state after an isolation step.Part (b) of FIG. 7 shows a structure obtained after forming theamorphous silicon of region 6 and an insulating film of region 12 as ahard mask for gate open, and removing regions 12 and 6 using the gateopen mask. If necessary, the process may be carried out with thepatterned photoresist that remains on the insulating film of region 12.

Part (c) of FIG. 7 shows that a portion of the silicon body of region 2for a channel region to be recessed has been partially etched using agate open mask. For surface protection in a subsequent process, aninsulating film having a thickness of 1-20 nm is selectively formed onthe surface of the recessed silicon body. As shown in part (d) of FIG.7, the nitride film of region 4 and the insulating film 3 are removed toexpose the surface and sides of the recessed silicon channel. Afterrecessing the channel, the formed selective insulating film is removed,and a process of improving the quality of the exposed silicon surface(suitable cleaning process or hydrogen annealing) is performed, and thenthe gate insulating film of region 7 is formed.

In carrying out the processes shown in parts (c) and (d) of FIG. 7,regions 2 and 6 may also be etched in reverse order. Although not shownin the drawings, the field insulating film may also be recessed to makethe structure of FIG. 3. Part (e) of FIG. 7 shows a structure obtainedafter forming and planarizing a gate electrode material. Part (f) ofFIG. 7 shows that regions 6 and 12 have been selectively removed.Subsequent processes includes spacer formation, silicide formation (ifnecessary), insulating film formation, contact formation, metalinterconnection, and the like, and are performed in a manner similar tothe existing processes. In the embodiment shown in FIG. 7, channeldoping can be performed following the process shown in part (a), (c) or(d) of FIG. 7. If the channel doping is performed following the processshown in part (c) or (d) of FIG. 7, it can be selectively performed onlyin the recessed region. Source/drain doping is preferably carried outfollowing the process shown in part (f) of FIG. 7. In some cases, ionimplantation for source/drain doping is carried out throughout thesilicon body of region 2 as shown in part (a) of FIG. 7, and a regionwhich will serve as a channel is selectively etched, wherebysource/drain regions, isolated from each other, can be made.

Following the process shown in part (f) of FIG. 7, an insulating filmspacer may be formed to a thickness of 5-200 nm. Preferably, the spacermaterial is formed to completely cover the gate electrode shown as d1 inFIG. 2( a). By doing so, in a process of performing metalinterconnection after forming an insulating film and forming a contacthole, the gate electrode and a metal filled in the contact hole forinterconnection metal are not short-circuited with each other. In theembodiment shown in FIG. 7, the materials of regions 6 and 12 is used tomake a self-aligned gate stack, and other materials having selectivitymay also be used.

FIG. 8 shows a structure capable of substituting for the structure shownin parts (a) and (b) of FIG. 7. An STI element isolation region isformed using the nitride film of region 4, and then fabricationprocesses similar to FIG. 7 are performed.

FIG. 9 shows an embodiment in which a thin oxide film is formed on thesurface of the silicon body in the structure shown in part (a) of FIG.7, followed by carrying out fabrication processes similar to FIG. 7. Forexample, the structure shown in part (a) of FIG. 9 is obtained byselectively etching the insulating film of region 5 in part (a) of FIG.8 up to the vicinity of the silicon surface and selectively removing thenitride film of region 4 up to the vicinity of the surface of thesilicon body.

FIG. 10 shows one method for forming the structure shown in part (a) ofFIG. 7. On the silicon substrate of region 1, the insulating film ofregion 11 is formed, after which the insulating film is removed using amask for defining the active body, and the silicon substrate is etchedto a suitable depth of less than 500 nm as shown in part (a) of FIG. 10,thus making the wall-type silicon body of region 2. In this case, aprocess for reducing the width of the silicon body may be additionallyperformed. Also, an annealing process for improving the sides of thesilicon body -may be carried out. Thereafter, the insulating film iscompletely removed, and then the insulating film of region 3 is formedto a thickness of more than 1 nm, on which the nitride film of region 4is formed. Then, a thick insulating film is formed and planarized,thereby forming the isolating oxide film of region 5 as shown in part(b) of FIG. 10. By a suitable planarization process, including thatmentioned in the description of FIG. 10, a structure shown in part (c)of FIG. 10 can be obtained.

INDUSTRIAL APPLICABILITY

As described above, the present invention relates to the MOS devicehaving a saddle structure. More particularly, the present inventionrelates to the high-integration/high-performance MOS device having anovel structure capable of improving the scaling-down characteristic andperformance of the MOS device, in which a channel and gate structure isformed in the form of a saddle. Thus, the present invention isindustrially applicable.

1. A MOS device comprising: a silicon substrate having formed thereon awall-type silicon body connected with the substrate; a first insulatingfilm formed on the surface of the silicon substrate and the surface ofthe silicon body; a nitride film formed on the first insulating film; asecond insulating film for element isolation formed on the nitride film;a region to be used as a channel, which is recessed from the surface ofthe silicon body to a given depth; the nitride film and the firstinsulating film around the recessed silicon body etched more than therecess width or depth of the silicon body; a gate insulating film formedon the surface and sides of the recessed silicon body; a gate electrodeand a spacer sequentially formed on the resulting structure; andsource/drain regions formed to a depth in the silicon body on both sidesof the gate electrode.
 2. The MOS device of claim 1, wherein, if thesilicon bodies made of single crystalline silicon are formed close toeach other, the surfaces of the first insulating film, the secondinsulating film and the nitride film (or the insulating film and thenitride film) between the silicon bodies formed within an adjacentdistance are formed lower than the surface of the recessed silicon bodyin a process of etching the insulating films to expose the sides of therecessed channel.
 3. A MOS device comprising: a silicon substrate havingformed thereon a wall-type silicon body connected with the substrate; afirst insulating film formed on the surface of the silicon substrate andthe surface of the silicon body; a nitride film formed on the firstinsulating film; a second insulating film for element isolation formedon the nitride film; a region to be used as a channel, which is recessedfrom the surface of the silicon body to a predetermined depth; thesecond insulating film being, if necessary, recessed from the surfacethereof to a predetermined depth; the nitride film and the firstinsulating film around the recessed silicon body etched more than therecess width or depth of the silicon body; a gate insulating film formedon the surface and sides of the recessed silicon body; a gate electrodeand a spacer sequentially formed on the resulting structure; andsource/drain regions formed to a depth in the silicon body on both sidesof the gate electrode.
 4. The MOS device of claim 3, wherein the siliconbody, the first insulating film, the nitride film and the secondinsulating film have recess widths or depths which vary along the gateelectrode.
 5. The MOS device of claim 1, wherein the recession depth ofthe second insulating film is in a range of 5-500 nm.
 6. The MOS deviceof claim 1, wherein the width of the silicon body including thesource/drain regions and the channel is in a range of 4-200 nm.
 7. TheMOS device of claim 1, wherein the height of the silicon body includingthe source/drain regions and the channel is in a range of 10-1000 nmfrom the surface of the silicon substrate.
 8. The MOS device of claim 1,wherein the silicon body is opened at a recess width of at least 10 nmand recessed to a depth of 5-500 nm.
 9. The MOS device of claim 1,wherein the bottom corners of the recessed channel formed in the siliconbody are formed at a right angle, an obtuse angle, an acute angle, orare rounded.
 10. The MOS device of claim 1, wherein the surface of therecessed region of the silicon body is formed with the channel of thedevice, and at the same time, the sides of the recessed channel surfaceare exposed at a length of 1-100 nm so as to serve as side channels. 11.The MOS device of claim 1, wherein the gate insulating film is formed onthe surface and sides of the recessed channel of the silicon body to thesame or different thicknesses in a range of 0.5-11 nm.
 12. The MOSdevice of claim 1, wherein the surface and sides of the recessed channelof the silicon body have angular shapes (corners), in which the angularshapes are formed at a right angle, an obtuse angle, an acute angle, orare rounded.
 13. The MOS device of claim 1, wherein the cross-sectionalshape of the silicon body is either narrow in width at the upper portionand then gradually wider toward the silicon substrate, or verticalaround a portion to be formed with the channel and then gradually widertoward the silicon substrate.
 14. The MOS device of claim 1, wherein thegate electrode is polysilicon, amorphous silicon, poly-SiGe, amorphousSiGe, a plurality of metals, a plurality of metal alloys, silicides withvarious metals, or a stack of said materials.
 15. The MOS device ofclaim 1, wherein the spacer is formed of a plurality of insulating filmsor a stack of said insulating films, and has a thickness of at least 5nm, with the thickness of the spacer being sufficient to cover the gateelectrode that is formed on the sides of the recessed silicon body andexposed on the surface of the silicon body.
 16. The MOS device of claim1, wherein the gate electrode is formed to almost the same height as thesurface of the silicon body, or formed above the surface of the body inthe form of self-alignment to a height of less than 500 nm.
 17. The MOSdevice of claim 1, wherein the transverse width of the gate electrodeformed above the silicon body is larger or smaller than the width formedbelow the surface of silicon body.
 18. The MOS device of claim 1,wherein the junction depth of the source/drain region is less than 500nm from the surface of the silicon body or is shallower than the recessdepth of the silicon body.
 19. The MOS device of claim 1, which furthercomprises an insulating film and a contact hole formed after forming thesource/drain regions and the insulating film spacer, in which thecontact hole can be formed to reach the insulating film spacer and isformed such that a metal layer can be contacted with the surface andsides of less than 400 nm of the silicon body having the source/drainregions formed therein, in order to reduce the contact resistancebetween the source/drain regions and metal wirings.
 20. The MOS deviceof claim 1, wherein the gate electrode is self-aligned with the recessedchannel using a hard mask selected from polysilicon, amorphous silicon,or an insulating film formed on polysilicon and amorphous silicon. 21.The MOS device of claim 1, wherein, before the gate insulating film isformed on the surface and sides of the recessed channel of the siliconbody, surface treatment including hydrogen annealing to improve thesurface properties of the silicon channel is carried out.
 22. The MOSdevice of claim 1, which has a structure formed by forming on thesilicon substrate the silicon body, the first insulating film, thenitride film and the second insulating film in order, planarizing thesurfaces of the first insulating film, the nitride film and the secondinsulating film up to the vicinity of the surface of the silicon body,and then selectively forming an insulating film on the surface of thesilicon body.
 23. The MOS device of claim 1, wherein, if the gateelectrode formed on the recessed nitride film causes stress with thenitride film, an insulating film for reducing stress is formed betweenthe nitride film and the gate electrode.
 24. The MOS device of claim 1,wherein a saddle-type flash device having a channel formed by exposingthe surface and side walls of the recessed silicon body using oneadditional mask, and a MOS device formed on the non-recessed surface ofthe silicon body, are integrated on the same chip.